Differential amplifier with large input common mode signal range

ABSTRACT

A design for a differential amplifier with a large input common mode signal range. The differential amplifier comprises two differential pairs, each having two amplifying MOSFETs. A source follower is connected to the gate terminal of each amplifying MOSFET in one of the differential pairs. A differential signal applied to the differential amplifier comprises two separate signal. Each separate signal is applied to the gate terminals of both the amplifying MOSFET in the differential pair not driven by the source follower and the driven MOSFET of the source follower. The differential amplifier further comprises a pair of switch MOSFETs connected to a current source MOSFET. The switch MOSFETs act to control the distribution of the total current flowing from the current source MOSFET and, consequently, to determine which differential pair works dominantly to amplify the input signals. Each source follower acts to offset the voltage of its input signal to compensate for the range loss due to the bias voltages and the threshold voltages within the differential amplifier.

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/256,126, filed Dec. 15, 2000, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of extending an inputsignal range of a component that receives the input signal.Specifically, the present invention relates to a design for an amplifierthat extends its input signal range. More specifically, the presentinvention relates to a design for a differential amplifier with a largeinput common mode signal range.

[0004] 2. Background Art

[0005] Operational amplifiers are key elements used in many analog andmixed analog/digital applications. Increasingly, these applications arebeing realized in smaller, portable packages, which require low powersupply voltages. This necessity taxes the ability of operationalamplifiers to provide the large voltage swings needed to ensure a widedynamic range.

[0006] Conventionally, operational amplifiers are implemented usingdifferential amplifiers to increase the voltage swing. The purpose of adifferential amplifier is to sense changes in its differential inputsignal while rejecting changes in its common mode, or average, inputsignal. By removing the common mode component of an input signal,differential amplifiers can support relatively large voltage swings.

[0007] Differential amplifiers are essential building blocks of mostmodern IC amplifiers and are predicated on the ability to fabricatematched transistors on a chip. Differential amplifiers are particularlyuseful for mixed signal applications where noise generated by digitalcircuits can distort analog signals. Noise appearing on both inputsignals of a differential circuit is rejected at the output signals.

[0008]FIG. 1 is a schematic diagram of a conventional differentialamplifier 100.

[0009] Differential amplifier 100 comprises two transistors “M₁” 102 and“M₂” 104 with source terminals connected together. A current source“I_(TAIL)” 106 is connected in parallel with a resistor “R_(TAIL)” 108between the source terminals and a first power supply voltage “V_(ss)”110. (In an embodiment, V_(ss) 110 could be analog ground.) A resistoris connected to the drain terminal of each transistor. “R_(D1)” 112 isconnected to the drain terminal of M₁ 102; “R_(D2)” 114 is connected tothe drain terminal of M₂ 104. R_(D1) 112 and R_(D2) 114 are togetherconnected to a second power supply voltage “V_(DD)” 116. (In anembodiment, V_(DD) 116 could be analog ground.) Differential amplifier100 receives a differential input signal and produces a differentialoutput signal. The differential input signal comprises a first inputsignal “v_(i1)” 118, which is applied to the gate terminal of M₁ 102,and a second input signal “v_(i2)” 120, which is applied to the gateterminal of M₂ 104. The differential output signal comprises a firstoutput signal “v₀₁” 122, which is produced at the drain terminal of M₂104, and a second output signal“v_(o2” 124, which is produced at the drain terminal of M) ₁ 102.Preferably, differential amplifier 100 is balanced such that eachcomponent on the side of one output (e.g., M_(l) 102, R_(D1) 112)corresponds to an identical component on the side of the other output(e.g., M₂ 104, R_(D2) 114).

[0010] M₁ 102 and M₂ 104 comprise a differential pair and act to controlthe distribution of current flowing from I_(TAIL) 106 between V_(DD) 116and V_(ss) 110. The sum of the current flowing through both M₁ 102 andM₂ 104 equals I_(TAIL) 106. So, for example, as v_(i1), 118 rises withrespect to v_(i2) 120, the portion of the total current of I_(TAIL) 106that flows through M₁ 102 and R_(D1) 112 increases, while the portionthat flows through M₂ 104 and R_(D2) 114 decreases. More current flowingthrough R_(D1) 112 increases the drop in voltage across R_(D1) 112,while less current flowing through R_(D2) 114 decreases the drop involtage across R_(D2) 114. Thus, v_(o1) 122 rises with respect to V_(o2)124.

[0011] The differential input signal can be expressed as shown in Eq.(1):

Eq. (1)V _(id) =V _(i1) −V _(i2),

[0012] while the common mode input signal can be expressed as shown inEq. (2):

Eq. (2)v _(ic) =[v _(il) +v _(i2)]/2.

[0013] Likewise, the differential output signal can be expressed asshown in Eq. (3):

Eq. (3)V _(od) =V _(o1) −V _(o2),

[0014] while the common mode output signal can be expressed as shown inEq. (4):

Eq. (4)v _(oc) =[v _(o1) +v _(o2)]/2.

[0015] As noted above, the purpose of differential amplifier 100 is tosense changes in its differential input signal v_(id) while rejectingchanges in its common mode input signal v_(ic). The ability ofdifferential amplifier 100 to realize this goal can be expressed byseveral figures of merit. Particularly, the common mode rejection ratio,CMRR, is defined as shown in Eq. (5):

Eq. (5) CMRR≡|A _(dm) /A _(cm)|,

[0016] where A_(dm) is the differential mode gain and A_(cm) is thecommon mode gain. A_(dm) can be expressed as shown in Eq. (6):

Eq. (6)A _(dm) =V _(od) /V _(id)|_(vic=0)={fraction (1/2 )}{[(v _(o1) −V_(o2))/V _(i1)]+[(V _(o2) −v _(o1))/V _(i2)]}.

[0017] A_(cm) can be expressed as shown in Eq. (7):

Eq. (7)A _(cm) =V _(oc) /V _(ic)|_(vid=o)=½{[(V _(o1) +v _(o2))/V_(i1)]+[(V _(o2) +V ₀₁)/V _(i2)]}.

[0018] In designing differential amplifiers, it is desired to maximizethe value of CMRR. This is indicative of maximizing the desireddifferential mode gain and/or minimizing the undesired common mode gain.Small signal analysis of a differential amplifier can be used to expressCMRR as a function of the physical parameters internal to thetransistors from which differential amplifier 100 is comprised. Thesmall signal analysis needs to account for both differential mode andcommon mode operations.

[0019]FIG. 2 is a schematic diagram of a small signal model circuit 200of differential amplifier 100. In circuit 200, M₁ 102 is modeled as acurrent source “i_(i)” 202 connected in parallel with an outputresistance “r_(o1)” 204 between a node “N₀” 206 and a node “N₁” 208. Aninput resistance “r_(π1)” 210 is connected in series between N_(o) 206and a first input signal “V_(i3)” 212. R_(D1), 112 is connected inseries between N₁ 208 and ground. A first output signal “v _(o3)” 214 isproduced at N₁ 208. Likewise, M₂ 104 is modeled as a current source “i₂”216 connected in parallel with an output resistance “r_(o2)” 218 betweenN_(o) 206 and a node “N₂” 220. An input resistance “r_(π2)” 222 isconnected in series between N_(o) 206 and a second input signal “V₁₄”224. A second output signal “v_(o4)” 226 is produced at N₂ 220. R_(D2)114 is connected in series between N₂ 220 and ground. R_(TAIL) 108 isconnected in series between N₀ 206 and ground.

[0020] The value of i₁ 202 can be expressed as shown in Eq. (8):

Eq. (8)i ₁ =g _(m) v ₁,

[0021] where g_(m) is the transconductance of M₁ 102 (or M₂ 104, becausedifferential amplifier 100 is balanced), and v, is the voltage dropacross r_(π1) 210.

[0022] Likewise, the value of i₂ 216 can be expressed as shown in Eq.(9):

Eq. (9)i ₂ =g _(m) V ₂,

[0023] where v₂ is the voltage drop across r_(π2) 222.

[0024] In differential mode, the value of v_(i3) 212 can be expressed asshown in Eq. (10):

Eq. (10)v _(i3) =v _(id)/2,

[0025] while the value of v_(i4) 224 can be expressed as shown in Eq.(11):

Eq. (11)V _(i4) =−V _(id)/2.

[0026] Likewise, the value of v_(o3) 214 can be expressed as shown inEq. (12):

Eq. (12)V _(o3) =v _(od)/2 ,

[0027] while the value of V_(o4) 226 can be expressed as shown in Eq. (13 ):

Eq. (13)v _(o4) =−v _(od)/2.

[0028] Where M₁ 102 and M₂ 104 are MOSFETs, input resistances rπ1 210and rπ2 222 are sufficiently large as to be considered infinite. Thus,the value of i_(i) 202 can be expressed as shown in Eq. (14):

Eq. (14)i ₁ =g _(m) v _(id)/2,

[0029] and the value of i₂ 216 can be expressed as shown in Eq. (15):

Eq. (15)i ₂ =−g _(m) v _(id)/2.

[0030] Because differential amplifier 100 is balanced and the inputsignals are driven by equal but opposite voltages, there is no variationin the voltage across R_(TAIL) 108. In small signal analysis, thiscondition is effectively the same as connecting N_(o) 206 to ground.Therefore, further analysis of small signal model circuit 200 operatingin differential mode can be simplified by analyzing a small signaldifferential mode model half circuit.

[0031]FIG. 3 is a schematic diagram of a small signal differential modemodel half circuit 300. In half circuit 300, i_(i) 202, r_(o1) 204, andR_(D1) 112 are connected in parallel between N₀ 206 and N₁ 208. N₀ 206is connected to ground. v_(o3) 214 is produced at N₁ 208. Recalling Eqs.(6), (12), and (14), A_(dm) can be expressed as shown in Eq. (16):

Eq. (16)A _(dm) =−g _(m) R,

[0032] where R is the effective resistance of the parallel combinationof r_(o1) 204 and R_(D1) 112.

[0033] Returning to FIG. 2, in common mode, the values of V_(i3) 212 andV_(i4) 224 can be expressed as shown in Eq. (17):

Eq. (17) V _(i3) =V _(i4) =V _(ic).

[0034] Likewise, the values of v_(o3) 214 and v_(o4) 226 can beexpressed as shown in Eq. (18):

Eq. (18)v _(o3) =v _(o4) =V _(oc).

[0035] Where M₁ 102 and M₂ 104 are MOSFETs, input resistances r_(π1) 210and r_(π2) 222 are sufficiently large as to be considered infinite.Thus, the values of i₁ 202 and i₂ 216 can be expressed as shown in Eq.(19):

Eq. (19)i ₁ =i ₂ =g _(m) V _(ic).

[0036] Because differential amplifier 100 is balanced and the inputsignals are driven by equal voltages, further analysis of small signalmodel circuit 200 operating in common mode can be simplified byanalyzing a small signal common mode model half circuit.

[0037]FIG. 4 is a schematic diagram of a small signal common mode modelhalf circuit 400. In half circuit 400, a resistor “R_(TAIL2)” 402 isconnected between N_(o) 206 and ground. The value of R_(TAIL2) 402 canbe expressed as shown in Eq. (20):

Eq. (20)R _(TAIL2)=2×R _(TAIL).

[0038] Conceptually, R_(TAIL) 108 in small signal model circuit 200 isfirst modeled as a parallel combination of two resistors connectedbetween N_(o) 206 and ground. Each resistor in the parallel combinationhas a resistance value equal to R_(TAIL2) 402, such that the resistancevalue of the parallel combination remains equal to R_(TAIL) 108. Thisenables small signal model circuit 200 to be reconfigured as smallsignal common mode model half circuit 400 so that it accounts for thevoltage drop across R_(TAIL) 108.

[0039] Also in half circuit 400, i₁ 202 is connected between N_(o) 206and N208 so that i₁ 202 and R_(TAIL2) 402 are connected in seriesbetween N₁ 208 and ground. Additionally, r_(o1) 204 and R_(D1) 112 areconnected in parallel between N₁ 208 and ground. v_(o3) 214 is producedat N₁ 208. Recalling Eqs. (7), (18), (19), and (20), A_(Cm) can beexpressed as shown in Eq. (21):

Eq. (21)A _(cm) =−g _(m) R/[1+g _(m) R _(TAIL2)],

[0040] where R is the effective resistance of the parallel combinationof r_(oI) 204 and R_(D1) 112.

[0041] Thus, recalling Eqs. (5), (16), and (21), CMRR, as a function ofthe physical parameters internal to the transistors from whichdifferential amplifier 100 is comprised, can be expressed as shown inEq. (22):

Eq. (22)CMRR =1+g _(m) R _(TAIL2).

[0042] In practical implementations, differential amplifiers arerealized using active devices for current sources, and in most casesalso for loads. Active devices provide large values of resistance, whiledropping less voltage and consuming less die area than passiveresistors.

[0043]FIG. 5 is a schematic diagram of a conventional differentialamplifier 500 with active loads. Differential amplifier 500 comprises adifferential pair 502 of air amplifying transistors M₁ 102 and M₂ 104with source terminals connected together. A load transistor is connectedto the drain terminal of each amplifying transistor. “M₃” 504 isconnected to the drain terminal of M₁ 102; “M₄” 506 is connected to thedrain terminal of M₂ 104. M₃ 504 and M₄ 506 are together connected topower supply voltage V_(DD) 116. A first bias voltage “V_(biasp)” 508holds load transistors M₃ 504 and M₄ 506 in saturation. A fifthtransistor “M₅” 510 provides a current source for differential amplifier500. M₅ 510 is connected between the source terminals of M₁ 102 and M₂104, and power supply voltage V_(ss) 110. A second bias voltage“V_(biasn)” 512 holds transistor M₅ 510 in saturation. First inputsignal v_(i1) 118 is applied to the gate terminal of M_(l) 102 and firstoutput signal v_(o1) 122 is produced at the drain terminal of M₂ 104.Second input signal v_(i2) 120 is applied to the gate terminal of M₂ 104and second output signal v_(o2) 124 is produced at the drain terminal ofM₁ 102.

[0044] In differential amplifier 500, M₁ 102, M₂ 104, and M₅ 510 areNMOSFETs, while M₃ 504 and M₄ 506 are PMOSFETs. However, one skilled inthe art would recognize that other transistor configurations could alsobe used. Preferably, differential amplifier 500 is balanced such thateach component on the side of one output (e.g., M₁ 102, M₃ 504)corresponds to an identical component on the side of the other output(e.g., M₂ 104, M₄ 506).

[0045] Unfortunately, while the use of active devices for currentsources and loads has several advantages, it also presents the problemof limiting the input common mode signal range. (It is desirable to havethe input common mode signal range from V_(ss) to V_(DD).) This is dueto the need to hold current source transistors in saturation. Thiscommon mode confinement is particularly difficult in applicationsseeking to meet, for example, IEEE Std 1596.3-1996 for LowVoltageDifferential Signals for Scalable Coherent Interface, which requires alarge input common mode signal range. An analysis of the input commonmode signal range for differential amplifier 500 highlights thislimitation.

[0046] For differential amplifier 500, the lower limit of v_(i), can beexpressed as shown in Eq. (23):

Eq. (23)v _(ic) >V _(ss) +v _(Tn) +V _(OVM5),

[0047] where v_(Tn) is the threshold voltage of M_(l) 102 (or M₂ 104),and v_(ovm5) is the A overdrive voltage of M₅ 510.

[0048] Likewise, the upper limit ofv_(ic can be expressed as shown in Eq. ()24):

Eq. (24)V _(ic) <V _(DD) +V _(Tn) −V _(ovload),

[0049] where v_(ovload) is the overdrive voltage of M₃ 504 (or M₄ 506).Normally, v_(Tn) >v _(ovload). Thus, the analysis shows that, while theupper limit of the input common mode signal range desirably can bemaintained greater than or equal to V_(DD), the lower limit of the inputcommon mode signal range undesirably often must be greater than V_(ss).

[0050] Conventionally, this problem has been addressed by configuring adifferential amplifier to have two differential pairs to increase theinput common mode signal range. FIG. 6 is a schematic diagram of aconventional differential amplifier 600 with two differential pairs.Differential amplifier 600 comprises differential pair 502 of amplifyingtransistors M₁ 102 and M₂ 104 with source terminals connected together.M₅ 510 is connected between V_(ss) 110 and the source terminals of M₁102 and M₂ 104. V_(biasn) 512 holds transistor M₅ 510 in saturation.

[0051] Differential amplifier 600 further comprises a seconddifferential pair 602 of amplifying transistors “M₆” 604 and “M₇” 606with source terminals connected together. A sixth transistor “M₈” 608provides a current source for amplifying transistors M₆ 604 and M₇ 606.M₈ 608 is connected between V_(DD) 116 and the source terminals M₆ 604and M₇ 606. A third bias voltage “V_(biasp2)” 610 holds transistor M₈608 in saturation.

[0052] First input signal v_(i1) 118 is applied to the gate terminals ofboth M₁ 102 and M₆ 604. Second input signal V_(i2) 120 is applied to thegate terminals of both M₂ 104 and M₇ 606. First output signal v_(oI) 122is produced at the drain terminal of M₂ 104. Second output signal V_(o2)124 is produced at the drain terminal of M₁ 102. A third output signal“v_(o5) ” 612 is produced at the drain terminal of M₇ 606. A fourthoutput signal “v_(o6) ” 614 is produced at the drain terminal of M₆ 604.

[0053] Differential amplifier 600 requires a subsequent stage, usually acascode structure, to provide loads for amplifying transistors M₁ 102,M₂ 104, M₆ 604, and M₇ 606, and to process the four output signalsv_(o1) 122, v_(o2) 124, v_(o5) 612, and v_(o6) 614.

[0054] In differential amplifier 600, M₁ 102, M₂ 104, and M₅ 510 areNMOSFETs, while M₆ 604, M₇ 606, and M₈ 608 are PMOSFETs. However, oneskilled in the art would recognize that other transistor configurationscould also be used. Preferably, differential amplifier 600 is balancedsuch that each component on the side of one output (e.g., M₁ 102, M₆604) corresponds to an identical component on the side of the otheroutput (e.g., M₂ 104, M₇ 606).

[0055] An analysis of the input common mode signal range fordifferential amplifier 600 shows that it is wider than that ofdifferential amplifier 500. For differential amplifier 600, the lowerlimit of v_(ic) can be expressed as shown in Eq. (25):

Eq. (25)V _(ic) >V _(SS) +V _(TP) +V _(ovloadn),

[0056] where V_(TP) is the threshold voltage of M₆ 604 (or M₇ 606), andV_(ovloadn) is the overdrive voltage of a NMOSFET load in the subsequentstage (not shown). Normally, V_(Tp)<0, but |V_(TP)|>|V_(ovloadn)|.

[0057] Likewise, the upper limit of v_(ic) can be expressed as shown inEq. (26):

Eq. (26)V _(ic) <V _(DD) +V _(Tn) −V _(ovloadp),

[0058] where v_(ovloadp) is the overdrive voltage of a PMOSFET load inthe subsequent stage (not shown). Thus, when V_(ovloadn)=V_(ovM5) andV_(ovloadp)=v_(ovload), comparisons of Eq. (23) with Eq. (25), and Eq.(24) with Eq. (26) show that the upper limit of the input common modesignal range desirably can be maintained greater than or equal toV_(DD), and the lower limit of the input common mode signal rangedesirably can also be maintained less than or equal to V_(ss).

[0059] However, while differential amplifier 600 maximizes the inputcommon mode signal range, the design presents several problems thatdetract from its usefulness. Significant power is dissipated andvaluable substrate area is consumed to support the second current sourcetransistor and to support the subsequent stage needed to provide loadsfor the amplifying transistors and to process the two additional outputsignals. Also, successful implementation of differential amplifier 600depends on an ability to fabricate differential pairs 502 and 602 withmatching gains and similar transient behaviors. This is very difficultto realize when differential pair 502 comprises NMOSFETs anddifferential pair 602 comprises PMOSFETs.

[0060] What is needed is a differential amplifier design that optimizesthe input common mode signal range, power dissipated, and substrate areaconsumed, and avoids the difficulty of matching gains between adifferential pair of NMOSFETs and a differential pair of PMOSFETs.

BRIEF SUMMARY OF THE INVENTION

[0061] The present invention relates to a method of extending an inputsignal range of a component that receives the input signal.Specifically, the present invention relates to a design for an amplifierthat extends its input signal range. More specifically, the presentinvention relates to a design for a differential amplifier with a largeinput common mode signal range.

[0062] The differential amplifier of the present invention comprises twodifferential pairs Each differential pair comprises two amplifyingMOSFETs with their source terminals connected together. The drainterminals of corresponding amplifying MOSFETs in each differential pairare also connected together and to the drain terminal of a correspondingload MOSFET. The amplifying MOSFETs are of the same type: eitherNMOSFETs or PMOSFETs. The load MOSFETs are of the type opposite that ofthe amplifying MOSFETs.

[0063] A bias voltage holds the load MOSFETs in saturation. The biasvoltage has the effect of limiting the voltages of an input common modesignal to a range less than the desirable voltage range. The desirablevoltage range spans between the voltages that supply power to theamplifier.

[0064] A source follower is connected to the gate terminal of eachamplifying MOSFET in one of the differential pairs. Each source followercomprises a driven MOSFET and a non-driven MOSFET. They are of the typeopposite that of the amplifying MOSFETs. The source terminal of eachdriven MOSFET and the drain terminal of the corresponding non-drivenMOSFET are connected to the gate terminal of the correspondingamplifying MOSFET. An input signal is applied at two terminals in eachhalf of the differential amplifier: the gate terminal of the drivenMOSFET of the source follower and the gate terminal of the amplifyingMOSFET not connected to the source follower. The source follower acts tooffset the voltage of the input signal to compensate for the range lossdue to the bias voltage.

[0065] The differential amplifier further comprises a pair of switchMOSFETs with their source terminals connected together and to a currentsource MOSFET. Another bias voltage holds the current source MOSFET insaturation. The drain terminal of one of the switch MOSFETs is connectedto the source terminals of the amplifying MOSFETs in the differentialpair driven by the source followers. A reference voltage is applied tothe gate terminal of this switch MOSFET. The drain terminal of the otherswitch MOSFET is connected to the source terminals of the amplifyingMOSFETs in the other differential pair. An input common mode signal isapplied to the gate terminal of this switch MOSFET. The other biasvoltage and the threshold voltages of the switch MOSFETs also have theeffect of limiting the voltages of the input common mode signal to arange less than the desirable voltage range.

[0066] The switch MOSFETs act to control the distribution of the totalcurrent flowing from the current source MOSFET. So, for example, whenthe input common mode signal voltage equals the reference voltage, equalportions of the total current flow through both switch MOSFETs; when theinput common mode signal voltage is greater than the reference voltage,a greater portion of the total current flows through the MOSFET switchtied to the differential pair directly driven by the input signals; andwhen the input common mode signal voltage is less than the referencevoltage, a greater portion of the total current flows through the MOSFETswitch tied to the differential pair driven by the source followers.

[0067] A differential input signal applied to the differential amplifiercomprises two separate signals. Each separate signal is applied to thegate terminals of both the amplifying MOSFET in the differential pairnot driven by the source follower and the driven MOSFET of the sourcefollower. Each source follower acts to offset the voltage of its inputsignal to compensate for the range loss due to the bias voltages and thethreshold voltages of the switch MOSFETs.

[0068] When equal portions of the total current flow through both switchMOSFETs, both differential pairs work equally to amplify the inputsignals; when a greater portion of the total current flows through theMOSFET switch tied to the differential pair directly driven by the inputsignals, that differential pair works dominantly; when a greater portionof the total current flows through the MOSFET switch tied to thedifferential pair driven by the source followers, that differential pairworks dominantly.

[0069] Advantageously, the differential amplifier optimizes its inputcommon mode signal range using differential pairs of the same type. Thismitigates difficulties faced in fabricating differential pairs withmatching gains and similar transient behaviors.

[0070] Furthermore, the differential amplifier does not require asubsequent stage to provide loads for its amplifying MOSFETs or toprocess additional output signals. Thus, it consumes both less power andless substrate area. Additional savings in power and substrate area arerealized because the differential pairs both draw current from the samecurrent source MOSFET.

[0071] Yet another advantage provided by the design of the differentialamplifier is a larger common mode rejection ratio because the switchMOSFETs are connected in a cascode configuration and act to maintain thetotal current more constant over the input common mode voltage range.

BRIEF DESCRIPTION OF THE FIGURES

[0072] The accompanying drawings, which are incorporated herein and formpart of the specification, illustrate the present invention and,together with the description, further serve to explain the principlesof the invention and to enable a person skilled in the pertinent art tomake and use the invention.

[0073]FIG. 1 is a schematic diagram of a conventional differentialamplifier 100.

[0074]FIG. 2 is a schematic diagram of a small signal model circuit 200of differential amplifier 100.

[0075]FIG. 3 is a schematic diagram of a small signal differential modemodel half circuit 300.

[0076]FIG. 4 is a schematic diagram of a small signal common mode modelhalf circuit 400.

[0077]FIG. 5 is a schematic diagram of a conventional differentialamplifier 500 with active loads.

[0078]FIG. 6 is a schematic diagram of a conventional differentialamplifier 600 with two differential pairs.

[0079]FIG. 7 is a schematic diagram of a differential amplifier 700configured to be a NMOSFET embodiment of the present invention.

[0080]FIG. 8 is a schematic diagram of a small signal model circuit 800of differential pair 502 of differential amplifier 700.

[0081]FIG. 9 is a schematic diagram of a circuit 900 for obtainingv_(ic) 736 from v_(il) 118 and v_(i2) 120.

[0082]FIG. 10 is a schematic diagram of a differential amplifier 1000configured to be a PMOSFET embodiment of the present invention.

[0083]FIG. 11 is a schematic diagram of a single-input amplifier 1100 ofthe present invention.

[0084]FIG. 12 shows a flow chart of a method 1200 for extending an inputsignal range of a component that receives a signal.

[0085] The preferred embodiments of the invention are described withreference to the figures where like reference numbers indicate identicalor functionally similar elements. Also in the figures, the left mostdigit of each reference number identifies the figure in which thereference number is first used.

DETAILED DESCRIPTION OF THE INVENTION

[0086] The present invention relates to a method of extending an inputsignal range of a component that receives the input signal.Specifically, the present invention relates to a design for an amplifierthat extends its input signal range.

[0087] More specifically, the present invention relates to a design fora differential amplifier with a large input common mode signal range.

[0088]FIG. 7 is a schematic diagram of a differential amplifier 700configured to be a NMOSFET embodiment of the present invention.Differential amplifier 700 comprises first differential pair 502 ofamplifying NMOSFETs M₁ 102 and M₂ 104 with source terminals connected ata first node “N₃” 702, and a second differential pair 704 of amplifyingNMOSFETs “M₉” 706 and “M₁₀” 708 with source terminals connected at asecond node “N₄” 710. First and second differential pairs 502, 704 areconnected in parallel. The drain terminals of M₁ 102 and M₉ 706 areconnected at a third node “N₅”712; the drain terminals of M₂ 104 and M₁₀708 are connected at a fourth node “N₆”714. M₃ 504 is connected as aload PMOSFET between V_(DD) 116 and N₅ 712; M₄ 506 is connected as aload PMOSFET between V_(DD) 116 and N₆ 714. First bias voltage V_(biasp)508 holds M₃ 504 and M₄ 506 in saturation.

[0089] A first switch NMOSFET “M₁₁” 716 and a second switch NMOSFET“M₁₂” 718 have their source terminals connected at a fifth node “N₇”720. The drain terminal of M₁₁ 716 is connected to N₃ 702; the drainterminal of M₁₂ 718 is connected to N₄ 710. M₁₁ 716 and M₁₂ 718 togethercomprise a differential switch circuit. Current source NMOSFET M₅ 510 isconnected between V_(ss) 110 and N₇ 720. Second bias voltage V_(biasn)512 holds M₅ 510 in saturation.

[0090] The source terminal of a first voltage offset PMOSFET “M₁₃” 722is connected with the gate terminal of M₉ 706 at a sixth node “N₈” 724.The drain terminal of M₁₃ 722 is connected to V_(ss) 110. A secondcurrent source PMOSFET “M ₁₄” 726 is connected between V_(DD) 116 and N₈724. The source terminal of a second voltage offset PMOSFET “M₁₅” 728 isconnected with the gate terminal of M₁₀ 708 at a seventh node “N₉” 730.The drain terminal of M₁₅ 728 is connected to V_(ss) 110. A thirdcurrent source PMOSFET “M₁₆” 732 is connected between V_(DD) 116 and N₉730. A third bias voltage “V_(biasp3)” 734 holds both M₁₄ 726 and M₁₆732 in saturation.

[0091] First input signal v_(i1) 118 is applied to the gate terminals ofboth M₁ 102 and M₁₃ 722 at a first input terminal “N₁₀” 736; secondinput signal v₁₂ 120 is applied to the gate terminals of both M₂ 104 andM₁₅ 730 at a second input terminal “N₁₁” 738. N₁₀ 736 and N₁₁ 738together comprise a differential input. First output signal v_(o1) 122is produced at N₆ 714, which is a first output terminal; second outputsignal V_(o2) 124 is produced at N₅ 712, which is a second outputterminal. N₆ 714 and N₅ 712 together comprise a differential output. Aninput common mode signal (see Eq. (2)) “v_(ic)” 747 is applied to thegate terminal of M₁₁ 716; a reference voltage “v_(ref) ” 742 is appliedto the gate terminal of M₁₂ 718.

[0092] Preferably, differential amplifier 700 is balanced such that eachcomponent on the side of one output (e.g., M₁ 102, M₃ 504, M₉ 706, M₁₁716, M₁₃ 722, M₁₄ 726) corresponds to an identical component on the sideof the other output (e.g., M₂ 104, M₄ 506, M₁₀ 708, M₁₂ 718, M₁₅ 728,M₁₆ 732).

[0093] Configured as they are, M₁₃ 722 and M₁₄ 726 form a first sourcefollower 744, where M₁₃ 722 is the driven PMOSFET and M₁₄ 726 is thenon-driven PMOSFET. Thus, the voltage at N₈ 724, V_(N8), can beexpressed as shown in Eq. (27):

Eq. (27)V _(N8) =V _(il) −V _(TpM13) +v _(ovM13),

[0094] where V_(TpM13) is the threshold voltage of M₁₃, and v_(ovM13) isthe overdrive voltage of M₁₃. Likewise, M₁₅ 728 and M₁₆ 732 form asecond source follower 746, where M₁₅ 728 is the driven PMOSFET and M₁₆732 is the non-driven PMOSFET. Thus, the voltage at N₉ 730, v_(N9), canbe expressed as shown in Eq. (28):

Eq. (28)V _(N9) =V _(i2) −V _(TpM15) +V _(ovM15),

[0095] where v_(TpMl5) is the threshold voltage of M₁₅, and V_(ovM15) isthe overdrive voltage of M₁₅. Normally, V_(TpM13)<0, and V_(TpM15) <0.Thus, M₁₃ 722 and M₁₅ 728 act to level shift, respectively, v_(il) 118and V_(i2) 120, by the sum of the absolute values of the threshold andoverdrive voltages of M₁₃ 722 (or equivalently, M₁₅, 728). First andsecond source followers 744, 746 together comprise a differential offsetcircuit.

[0096] First differential pair 502 directly amplifies v_(il) and v_(i2),while second differential pair 704 amplifies V_(N8) and V_(N9). Hence,second differential pair 704 indirectly amplifies v_(i1) and V_(i2)because of the voltage drop across M₁₃ 722 and M₁₅ 728. Based on theinstantaneous value of v_(ic) 736, M₁₁ 716 and M₁₂ 718 act to controlwhich of first and second differential pairs 502, 704 dominates theother during amplification. The effect of this arrangement is that eachdifferential pair 502, 704 has its own corresponding input common modesignal range such that the overall input common mode signal range ofdifferential amplifier 700 is improved. For example, first differentialpair 502 dominates over a first input common mode signal range, andsecond differential pair 704 dominates over a second input common modesignal range.

[0097] M₁₁ 716 controls a first current flow to first differential pair502 based on As v_(ic) 740. Likewise, M₁₂ 718 controls a second currentflow to second differential pair 704. Therefore, M₁₁ 716 and M₁₂ 718determine the respective gain of differential pairs 502, 704. The sum ofcurrent flowing through both M₁₁ 716 and M₁₂ 718 equals the totalcurrent flowing through M₅ 510. So, for example, when v_(ic) 740 equalsv_(ref) 742, equal portions of the total current flow through M₁₁ 716and M₁₂ 718; when v_(ic) 740 is greater than v_(ref) 742, a greaterportion of the total current flows through M₁₁ 716; and when V_(ic) 740is less than v_(ref) 742, a greater portion of the total current flowsthrough M₁₂ 718.

[0098] When equal portions of the total current flow through both M₁₁716 and M₁₂ 718, both differential pairs 502, 704 provide equalamplification for v_(il) and v_(i2). When a greater portion of the totalcurrent flows through M₁₁ 716, first differential pair 502 provides moreamplification than second differential pair 704. When a greater portionof the total current flows through M₁₂ 718, second differential pair 704provides more amplification than first differential pair 502.

[0099] In an embodiment, v_(ref) 740 is set at a voltage level greaterthan the lower limit of the input common mode signal range ofdifferential pair 502. However, the skilled artisan would recognizeother voltage levels to which v_(ref) 740 could be set.

[0100] An analysis of the input common mode signal range fordifferential amplifier 700 shows that it is wider than that ofdifferential amplifier 500. For differential amplifier 700, the lowerlimit of v_(ic) can be expressed as shown in Eq. (29):

Eq. (29)V _(ic) >V _(SS) +V _(Tn2) +V _(ovM5) +V _(dSMI2) −V _(poffset),

[0101] where V_(Tn2) is the threshold voltage of M₉ 706 (or M₁₀ 708),V_(ovM5) is the overdrive voltage of M₅ 510, v_(dsM12) is thedrain-to-source voltage of M₁₂ 718, and v_(poffset) is the sum of theabsolute values of the threshold and overdrive voltages of M₁₃ 722 (orM₁₅ 728). M₁₂ 718 works in the linear region as a switch. It is possiblethat V_(poffset)>V_(Tn2)+V_(ovM5)+V_(dSMI2).

[0102] Likewise, the upper limit of v_(ic) can be expressed as shown inEq. (30):

Eq. (30)V _(ic) <V _(DD) +V _(Tn) −V _(ovload),

[0103] where v_(Tn) is the threshold voltage of M₁ 102 (or M₂ 104), andv_(ovload) is the overdrive voltage of M₃ 504 (or M₄ 506). By comparingEq. (23) with Eq. (29), it can be seen that the upper limit of the inputcommon mode signal range desirably can be maintained greater than orequal to V_(DD). Similarly, by comparing Eq. (24) with Eq. (30), it canbe seen that the lower limit of the input common mode signal rangedesirably can be maintained less than or equal to V_(ss).

[0104] Advantageously, differential amplifier 700 optimizes its inputcommon mode signal range using differential pairs of NMOSFETs. Thismitigates difficulties faced in fabricating differential pairs withmatching gains and similar transient behaviors.

[0105] Also, unlike differential amplifier 600, differential amplifier700 does not require a subsequent stage to provide loads for itsamplifying transistors or to process additional output signals. Thus, incomparison with differential amplifier 600, differential amplifier 700consumes both less power and less substrate area.

[0106] Further savings in power and substrate area are realized becausedifferential pairs 502, 704 both draw current from current sourcetransistor M₅ 510. While differential amplifier 700 does include currentsource transistors M₁₄ 726 and M₁₆ 732, these devices are sized at anorder of magnitude (about ten times) smaller than that of current sourcetransistor M₈ 608 in differential amplifier 600. Therefore, whencorresponding devices of differential amplifiers 600 and 700 aresimilarly sized, differential amplifier 700 consumes less power andoccupies less substrate area.

[0107] Yet another advantage provided by the design of differentialamplifier 700, in comparison with differential amplifier 600, is alarger CMRR. Recalling that the CMRR of differential amplifier 100 wasderived through analysis of small signal model circuit 200 in FIG. 2, asimilar analysis can be performed on a small signal model circuit fordifferential amplifier 700 to derive its CMRR.

[0108]FIG. 8 is a schematic diagram of a small signal model circuit 800of differential pair 502 of differential amplifier 700. Becausedifferential pair 502 includes amplifying transistors M₁ 102 and M₂ 104,which are common to differential amplifiers 100, 600, and 700, smallsignal model circuit 800 is similar to the topology of small signalmodel circuit 200 with some differences as explained below.

[0109] While differential amplifier 100 uses resistors R_(D1) 112 andR_(D2) 114 for passive loads, differential amplifier 700 usestransistors M₃ 504 and M₄ 506 for active loads. Thus, R_(D1) 112 incircuit 200 is replaced in circuit 800 by a resistor “r_(OM3)” 802,which corresponds to the output resistance of M₃ 504. Likewise, R_(D2)114 in circuit 200 is replaced in circuit 800 by a resistor “r_(OM4)”804, which corresponds to the output resistance of M₄ 506. A smallsignal model circuit for differential amplifier 600 (not shown) wouldinclude a similar replacement.

[0110] Similarly, while differential amplifier 100 uses (ideal) currentsource I_(TAIL) 106 connected in parallel with resistor R_(TAIL) 108,differential pair 502 (in both differential amplifiers 600 and 700) usescurrent source transistor M₅ 510. Thus, R_(TAIL) 108 in circuit 200 isreplaced in circuit 800 by a resistor “r_(0M5)” 806, which correspondsto the output resistance of M₅ 510.

[0111] However, unlike differential amplifiers 100 or 600, differentialamplifier 700 also includes switch transistors M₁₁ 716 and M₁₂ 718.Therefore, circuit 800 also includes a resistor “r_(0M11)” 808, whichcorresponds to the output resistance of M₁₁ 716, connected in serieswith r_(0M5) 806 between N₀ 206 and ground.

[0112] So, while analysis of small signal model circuit 200 yielded Eq.(22) as an expression for the CMRR of differential amplifiers 100 and600, a parallel analysis of small signal model circuit 800 shows thatthe CMRR of differential pair 502 of differential amplifier 700 can beexpressed as shown in Eq. (31):

Eq. (31)CMRR=[1+2g _(m×() r _(0M5) +r _(0M11))],

[0113] A similar analysis of differential pair 704 shows that its CMRRcan be expressed as shown in Eq. (32):

Eq. (32)CMRR=[1 +2g _(m×() r _(0MS) +r _(0M12))],

[0114] where r_(0M12) is the output resistance of M₁₂ 718. (Normally,r_(0M11 =r) _(0M12).) Thus, the CMRR of differential amplifier 700 islarger than that of differential amplifiers 100 or 600, when(R_(0MS)+r_(0M12)) >R_(TAIL).

[0115]FIG. 9 is a schematic diagram of a circuit 900 for obtainingv_(ic) 740 from v_(il) 118 and V_(i2) 120. In circuit 900, a firstdivision resistor “R_(div1)” 902 is connected in series between a firstnode “N₁₂” 904 and a second node “N₁₃” 906. A second division resistor“R_(diV2)” 908 is connected in series between N₁₃ 906 and a third node“N₁₄” 910. The resistance of R_(div1) equals the resistance of R_(diV2).First input signal v_(il) 118 is applied to N₁₂ 904; second input signalV_(i2) 120 is applied to N₁₄ 910. Input common mode signal v_(ic) 740 isproduced at N₁₃ 906. One skilled in the art would recognize other meansby which v_(ic) 740 could be obtained from v_(il) 118 and V_(i2) 120.The present invention is not limited to use of circuit 900.

[0116]FIG. 10 is a schematic diagram of a differential amplifier 1000configured to be a PMOSFET embodiment of the present invention.Differential amplifier 1000 comprises first differential pair 602 ofamplifying PMOSFETs M₆ 604 and M₇ 606 with source terminals connected ata first node “N₁₃” 1002, and a second differential pair 1004 ofamplifying PMOSFETs “M_(l7)” 1006 and “M₁₈” 1008 with source terminalsconnected at a second node “N₁₄” 1010. First and second differentialpairs 602, 1004 are connected in parallel. The drain terminals of M₆ 604and M₁₇ 1006 are connected at a third node “N₁₅ ” 1012; the drainterminals of M₇ 606 and M₁₈ 1008 are connected at a fourth node “N₁₆”1014. A first load transistor “M₁₉” 1016 is connected as a load NMOSFETbetween V_(SS) 110 and N₁₅ 1012; a second load transistor “M₂₀” 1018 isconnected as a load NMOSFET between V_(ss) 110 and N₁₆ 1014. A firstbias voltage “V_(biasn2)” 1020 holds M₁₉ 1016 and M₂₀ 1018 insaturation.

[0117] A first switch PMOSFET “M₂₁” 1022 and a second switch PMOSFET“M₂₂” 1024 have their source terminals connected at a fifth node “N₁₇”1026. The drain terminal of M₂₁ 1022 is connected to N₁₃ 1002; the drainterminal of M₂₂ 1024 is connected to N₁₄ 1010. M₂₁ 1022 and M₂₂ 1024together comprise a differential switch circuit. Current source PMOSFETM₈ 608 is connected between V_(DD) 116 and N₁₇ 1026. Second bias voltageV_(biasp2) 610 holds M₈ 608 in saturation.

[0118] The source terminal of a first voltage offset NMOSFET “M₂₃” 1028is connected with the gate terminal of M₁₇ 1006 at a sixth node “N₁₈”1030. The drain terminal of M₂₃ 1028 is connected to V_(DD) 116. Asecond current source NMOSFET “M₂₄” 1032 is connected between V_(ss) 110and N₁₈ 1030. The source terminal of a second voltage offset NMOSFET“M₂₅” 1034 is connected with the gate terminal of M₁₈ 1008 at a seventhnode “N₁₉” 1036. The drain terminal of M₂₅ 1034 is connected to V_(DD)116. A third current source NMOSFET “M₂₆” 1038 is connected betweenV_(ss) 110 and N₁₉ 1036. A third bias voltage “V_(biasn3)” 1040 holdsboth M₂₄ 1032 and M₂₆ 1038 in saturation.

[0119] First input signal v_(i1) 118 is applied to the gate terminals ofboth M₆ 604 and M₁₇ 1006 at a first input terminal “N₂₀” 1042; secondinput signal v_(i2) 120 is applied to the gate terminals of both M₇ 606and M₁₈ 1008 at a second input terminal “N₂₁” 1044. N₂₀ 1042 and N₂₁,1044 together comprise a differential input. First output signal v_(o1)122 is produced at N₁₆ 1014, which is a first output terminal; secondoutput signal V_(o2) 124 is produced at N₁₅ 1012, which is a secondoutput terminal. N₁₆ 1014 and N₁₅ 1012 together comprise a differentialoutput.

[0120] Input common mode signal (see Eq. (2)) v_(ic) 740 is applied tothe gate terminal of M₂₁ 1022; reference voltage v_(ref) 742 is appliedto the gate terminal of M₂₂ 1024.

[0121] Preferably, differential amplifier 1000 is balanced such thateach component on the side of one output (e.g., M₆ 604, M₁₇ 1006, M₁₉1016, M₂₁ 1022, M₂₃ 1028, M₂₄ 1032) corresponds to an identicalcomponent on the side of the other output (e.g., M₇ 606, M₁₈ 1008, M₂₀1018, M₂₂ 1024, M₂₅ 1034, M₂₆ 1038).

[0122] Configured as they are, M₂₃ 1028 and M₂₄ 1032 form a first sourcefollower 1046, where M₂₃ 1028 is the driven NMOSFET and M₂₄ 1032 is thenon-driven NMOSFET. Thus, the voltage at N₁₈ 1030,V_(N18, can be expressed as shown in Eq. ()33):

Eq. (33)v _(NI8) =v _(il) −v _(TnM23) −v _(0vM23),

[0123] where v_(TnM23) is the threshold voltage of M₂₃, and V_(ovM23) isthe overdrive voltage of M₂₃. Likewise, M₂₅ 1034 and M₂₆ 1038 form asecond source follower 1048, where M₂₅ 1034 is the driven NMOSFET andM₂₆ 1038 is the non-driven NMOSFET. Thus, the voltage at N₁₉ 1036,v_(N19), can be expressed as shown in Eq. (34):

Eq. (34)v _(N19) =v _(i2) −v _(TnM25) −v _(ovM25),

[0124] where v_(TnM25) is the threshold voltage of M₂₅, andV_(ovM25 is the overdrive voltage of M) ₂₅. Thus, M₂₃ 1028 and M₂₅ 1034act to level shift, respectively, v_(i1) 118 and v_(i2) 120, the sum ofthe absolute values of the threshold and overdrive voltages of M₂₃ 1028(or equivalently, M₂₅ 1034). First and second source followers 1046,1048 together comprise a differential offset circuit.

[0125] First differential pair 602 directly amplifies v_(il) and v_(i2),while second differential pair 1004 amplifies V_(N18) and v_(N19).Hence, second differential pair 1004 indirectly amplifies v_(il) andv_(i2) because of the voltage drop across M₂₃ 1028 and M₂₅ 1034. Basedon the instantaneous value of v_(ic) 736, M₂₁ 1022 and M₂₂ 1024 act tocontrol which of first and second differential pairs 602, 1004 dominatesthe other during amplification. The effect of this arrangement is thateach differential pair 602, 1004 has its own corresponding input commonmode signal range such that the overall input common mode signal rangeof differential amplifier 1000 is improved. For example, firstdifferential pair 602 dominates over a first input common mode signalrange, and second differential pair 1004 dominates over a second inputcommon mode signal range.

[0126] M₂₁ 1022 controls a first current flow to first differential pair602 based on v_(ic) 740. Likewise, M₂₂ 1024 controls a second currentflow to second differential pair 1004. Therefore, M₂₁ 1022 and M₂₂ 1024determine the respective gain of differential pairs 602, 1004. The sumof current flowing through both M₂₁ 1022 and M₂₂ 1024 equals the totalcurrent flowing through M₈ 608. So, for example, when v_(ic) 740 equalsv_(ref) 742, equal portions of the total current flow through M₂₁ 1022and M₂₂ 1024; when v_(ic) 740 is less than v_(ref) 742, a greaterportion of the total current flows through M₂₁ 1022; and when v_(ic) 740is greater than v_(ref) 742, a greater portion of the total currentflows through M₂₂ 1024.

[0127] When equal portions of the total current flow through both M₂₁1022 and M₂₂ 1024, both differential pairs 602, 1004 provide equalamplification for vil and v_(i2). When a greater portion of the totalcurrent flows through M₂₁ 1022, first differential pair 602 providesmore amplification than second differential pair 1004. When a greaterportion of the total current flows through M₂₂ 1024, second differentialpair 1004 provides more amplification than first differential pair 502.

[0128] In an embodiment, v_(ref) 740 is set at a voltage level lesserthan the upper limit of the input common mode signal range ofdifferential pair 602. However, the skilled artisan would recognizeother voltage levels to which v_(ref) 740 could be set.

[0129] An analysis of the input common mode signal range fordifferential amplifier 1000 shows that it is wider than that ofdifferential amplifier 500. For differential amplifier 1000, the lowerlimit of vi, can be expressed as shown in Eq. (35):

Eq. (35)v _(ic) >V _(ss) +v _(Tp2) +V _(ovload2),

[0130] where v_(Tp2) is the threshold voltage of M₆ 604 (or M₇ 606), andv_(ovload2) is the overdrive voltage of M₁₉ 1016 (or M₂₀ 1016).Normally, V_(Tp2)<0, but |V_(Tp2|>|V) _(ovload2)|.

[0131] Likewise, the upper limit of vi, can be expressed as shown in Eq.(36):

Eq. (36)V _(ic) <V _(DD) +V _(Tp3) −v _(ovMS) +V _(dsM22) +V _(noffset),

[0132] where V_(Tp3) is the threshold voltage of M₁₇ 1006 (or M₁₈ 1008),v_(ovM8) is the overdrive voltage of M₈ 608, v_(dSM22) is thedrain-to-source voltage of M₂₂ 1024, and v_(noffset) is the sum of theabsolute values of the threshold and overdrive voltages of M₂₃ 1028 (orM₂₅ 1034). Normally, v_(Tp3)<0 and v_(dsM22)<0. M₂₂ 1024 works in thelinear region as a switch. It is possible that v_(noffset >−v) _(Tp3) +v_(ovM8 +v) _(dsM22). By comparing Eq. (23) with Eq. (35), it can be seenthat the upper limit of the input common mode signal range desirably canbe maintained greater than or equal to V_(DD). Similarly, by comparingEq. (24) with Eq. (36), it can be seen that the lower limit of the inputcommon mode signal range desirably can also be maintained less than orequal to V_(ss).

[0133] The above explanation of the present invention has been in thecontext of employing it in a differential amplifier. However, in a moregeneral sense, the present invention relates to a method of extending aninput signal range of any component that receives a signal. The skilledartisan would appreciate that, in this general sense, the presentinvention can be realized in any number of embodiments in which acircuit first level shifts the voltage of the input signal and thenprocesses the input signal.

[0134]FIG. 11 is a schematic diagram of a single-input amplifier 1100 ofthe present invention. Single-input amplifier 1100 comprises firstamplifying transistor M₁ 102 and second amplifying transistor M₉ 706with drain terminals connected at first node N₅ 712. The sourceterminals of M_(I) 102 and M₉ 706 are connected to V_(ss) 110. Loadtransistor M₃ 504 is connected between V_(DD) 116 and N₅ 712. Inaddition to providing active load, M₃ 504 also acts as a current sourcefor single-input amplifier 1100. The source terminal of M₃ 504 isconnected to V_(DD) 116. First bias voltage V_(biasp) 508 holds M₃ 504in saturation. The source terminal of voltage offset transistor M₁₃ 722is connected with the gate terminal of M₉ 706 at second node N₈ 724. Thedrain terminal of M₁₃ 722 is connected to V_(ss) 110. Second currentsource transistor M₁₄ 726 is connected between V_(DD) 116 and N₈ 724.Second bias voltage V_(biasp3) 734 holds M₁₄ 726 in saturation.

[0135] Input signal v_(il) 118 is applied to the gate terminals of bothM₁ 102 and M₁₃ 722 at input terminal N₁₀ 736. Output signal V_(o2) 124is produced at N₅ 712, which is the output terminal. Configured as theyare, M₁₃ 722 and M₁₄ 726 forrn source follower 744, where M₁₃ 722 is thedriven MOSFET and M₁₄ 726 is the non-driven MOSFET. Thus, the voltage atN₈ 724, v_(N8), can be expressed as shown above in Eq. (27):

Eq. (27)v _(N8) =v _(i1) −v _(TpM13),

[0136] where v_(TpM13) is the threshold voltage of M₁₃. Normally,V_(TpM13)<0. Thus, M₁₃ 722 acts to level shift v_(i1) 118 by thethreshold voltage. Source follower 744 comprises an offset circuit.Thus, while M₁ 102 directly amplifies v_(i1) , M₉ 706 amplifies v_(N8).Hence, M₉ 706 indirectly amplifies v_(i1) because of the voltage dropacross M₁₃ 722.

[0137] For single-input amplifier 1100, the lower limit of v_(i1) 118can be expressed as shown in Eq. (37):

Eq. (37)v _(il) >V _(SS) +V _(Tn2) −V _(poffset),

[0138] where v_(T2) is the threshold voltage of M₉ 706, and v_(poffset)is the sum of the absolute values of the threshold and overdrivevoltages of M₁₃ 722. It is possible that V_(poffset)>V_(Tn2).

[0139] Likewise, the upper limit of v_(il) can be expressed as shown inEq. (38):

Eq. (38)v _(il) <V _(DD) +v _(Tn −v) _(ovload),

[0140] where v_(Tn) is the threshold voltage of M₁ 102, and v_(ovload)is the overdrive voltage of M₃ 504. Normally, v_(Tn)>v_(ovload). Thus,the upper limit of the input signal range desirably can be maintainedgreater than or equal to V_(DD), and the lower limit of the input signalrange desirably can also be maintained less than or equal to V_(ss).

[0141] In single-input amplifier 1100, M₁ 102 and M₉ 706 are NMOSFETs,while M₃ 504, M₁₃ 722, and M₁₄ 726 are PMOSFETs. However, one skilled inthe art would recognize that other transistor configurations could alsobe used.

[0142]FIG. 12 shows a flow chart of a method 1200 for extending an inputsignal range of a component that receives the input signal. In method1200, at a step 1202, a voltage of the input signal is level shifted.This is done to compensate the input signal for bias voltages within thecomponent that limit the voltages of the input signal to a range lessthan the desirable voltage range. The desirable voltage range spansbetween the voltages that supply power to the component. For example,offset transistors M₁₃ 722 and M₁₅ 728 level shift, respectively, inputsignals v_(il) 118 and v_(il) 120, by the threshold voltages.

[0143] Optionally, at a step 1204, a subcomponent from a plurality ofsubcomponents is selected to process the level shifted voltage. In anembodiment, the subcomponent is selected in response to a comparisonbetween a common mode voltage of the input signal and a referencesignal. For example, M₁₁ 716 controls the current flow to differentialpair 502 based on v_(ic) 736. Likewise, M₁₂ 718 controls the currentflow to differential pair 704. Based on the instantaneous value ofv_(ic) 736, M₁₁ 716 and M₁₂ 718 act to control which of differentialpairs 502, 704 dominates the other during amplification. When a greaterportion of the total current flows through M₁₂ 718, differential pair704 provides more amplification than differential pair 502. Thus,differential pair 704 is selected to process the level shifted voltage.

[0144] At a step 1206, the level shifted voltage is processed within thecomponent. In an embodiment, the offset voltage is amplified within thecomponent. For example, differential pair 704 amplifies V_(N8) andV_(N9), thus processing the level shifted voltages. Because of thevoltage drop across M₁₃ 722 and M₁₅ 728, differential pair 704indirectly amplifies v_(il) and v_(i2).

[0145] Conclusion

[0146] While various embodiments of the present invention have beendescribed above, it should be understood that they have been presentedby way of example, and not limitation. It would be apparent to personsskilled in the relevant art that various changes in form and detail canbe made therein without departing from the spirit and scope of theinvention. Thus the present invention should not be limited by any ofthe above-described exemplary embodiments, but should be defined only inaccordance with the following claims and their equivalents.

What is claimed is:
 1. A differential amplifier, comprising: adifferential input capable of receiving a differential signal; a firstdifferential pair coupled to said differential input; a seconddifferential pair, coupled to said differential input, and connected inparallel with said first differential pair at a differential output; anda differential offset circuit, coupled between said differential inputand said second differential pair, and capable of level shifting saiddifferential signal from a first level to a second level.
 2. Thedifferential amplifier of claim 1, further comprising: a differentialswitch circuit, coupled to said first differential pair and said seconddifferential pair, and capable of controlling a first current flow tosaid first differential pair and a second current flow to said seconddifferential pair.
 3. The differential amplifier of claim 1, whereinsaid differential offset circuit comprises: a first source followercoupled between a first input terminal of said differential input and afirst amplifying MOSFET of said second differential pair; and a secondsource follower coupled between a second input terminal of saiddifferential input and a second amplifying MOSFET of said seconddifferential pair.
 4. The differential amplifier of claim 1, whereinsaid first differential pair comprises a first MOSFET with a first drainterminal, and a second MOSFET with a second drain terminal, and saidsecond differential pair comprises a third MOSFET with a third drainterminal connected to said first drain terminal, and a fourth MOSFETwith a fourth drain terminal connected to said second drain terminal. 5.A differential amplifier, comprising: a differential input capable ofreceiving a differential signal; a first differential pair coupled tosaid differential input; a second differential pair, coupled to saiddifferential input, and connected in parallel with said firstdifferential pair at a differential output; and a differential switchcircuit, coupled to said first differential pair and said seconddifferential pair, and capable of controlling a first current flow tosaid first differential pair and a second current flow to said seconddifferential pair.
 6. The differential amplifier of claim 5, furthercomprising: a differential offset circuit, coupled between saiddifferential input and said second differential pair, and capable oflevel shifting said differential input signal from a first level to asecond level.
 7. The differential amplifier of claim 5, wherein saiddifferential switch circuit comprises: a first switch MOSFET coupledbetween said first differential pair and a current source; and a secondswitch MOSFET coupled between said second differential pair and saidcurrent source.
 8. A differential amplifier, comprising: a differentialinput capable of receiving a differential input signal; a firstdifferential pair coupled to said first differential input, said firstdifferential pair biased with a first power supply voltage and a secondpower supply voltage; a second differential pair, coupled to saiddifferential input, and connected in parallel with said firstdifferential pair at a differential output, said second differentialpair biased with said first power supply voltage and said second powersupply voltage; and a differential switch circuit, coupled to said firstdifferential pair and said second differential pair, and capable ofcontrolling a first current flow to said first differential pair and asecond current flow to said second differential pair.
 9. Thedifferential amplifier of claim 8, wherein said differential switchcircuit changes said first current flow relative to said second currentflow, based on a comparison between a common mode voltage of saiddifferential input signal and a reference voltage.
 10. The differentialamplifier of claim 8, wherein said differential switch circuit increasessaid first current flow relative to said second current flow, when acommon mode voltage of said differential input signal approaches saidfirst power supply voltage.
 11. The differential amplifier of claim 8,wherein said differential switch circuit decreases said first currentflow relative to said second current flow, when a common mode voltage ofsaid differential input signal approaches said second power supplyvoltage.
 12. An amplifier, comprising: an input capable of receiving aninput signal; a first amplifying MOSFET coupled to said input; a secondamplifying MOSFET, coupled to said input, and connected in parallel withsaid first amplifying MOSFET at an output; and an offset circuit,coupled between said input and said second amplifying MOSFET, andcapable of level shifting said input signal from a first level to asecond level.
 13. The amplifier of claim 12, wherein said offset circuitcomprises: a source follower coupled between said input and said secondamplifying MOSFET.
 14. The amplifier of claim 13, wherein said sourcefollower comprises: a third MOSFET with a source terminal connected to agate terminal of said second amplifying MOSFET; and a fourth MOSFET witha drain terminal connected to said gate terminal.
 15. The amplifier ofclaim 14, wherein said first amplifying MOSFET and said secondamplifying MOSFET are a first type that is one of a NMOSFET and aPMOSFET.
 16. The amplifier of claim 15, wherein said third MOSFET andsaid fourth MOSFET are a second type, said second type being opposite ofsaid first type.
 17. A method of extending an input signal range of acomponent that receives the input signal, comprising the steps of: (1)level shifting a voltage of the input signal; and (2) processing saidlevel shifted voltage within the component.
 18. The method of claim 17,wherein step (2) comprises the step of: amplifying said level shiftedvoltage within the component.
 19. The method of claim 17, furthercomprising the step of: (3) selecting a subcomponent, from a pluralityof subcomponents within the component, to process said offset voltage.20. The method of claim 19, wherein step (3) comprises the step of:responding to a comparison between a common mode voltage of the inputsignal and a reference voltage to select said subcomponent from saidplurality of subcomponents to process said offset voltage.